1. Field of the Invention
The present invention relates generally to a circuit and method for generating symmetric and complementary signals from a single signal, and more particularly, to a buffer/inverter.
2. Related Art
Various electronic circuits require symmetric and complementary clock signals. "Symmetric and complementary signals" are hereby defined to be two signals which at any point in time have voltage levels of approximately equal magnitude but of opposite polarity. Two clocks of the same frequency could generate such signals. However, synchronizing the clocks would be difficult.
A more common solution is to use a device called a buffer/inverter to generate symmetric and complementary signals from a single clock signal. Conventional buffer/inverters are implemented with a chain of an even number of inverters for generating a true signal and a chain of an odd number of inverters for generating a complement signal.
FIG. 1 is a schematic of a conventional buffer/inverter 100. An input terminal 104 is connected to the input of a first inverter 106. The output of the first inverter 106 is connected to the input of a second inverter 108. The output of the second inverter 108 is connected to a true output terminal 102.
The input terminal 104 is also connected to the input of a third inverter 112. The output of the third inverter is connected to a complement output terminal 110.
In an attempt to generate symmetric and complementary signals, conventional buffer/inverters are implemented with inverters in the longer chain having proportionately faster switching times than the inverter or inverters in the shorter chain. Thus, the first and second inverters 106, 108 would switch twice as fast as the third inverter 112.
The switching time of a FET inverter is approximately proportional to the dimensions of its channel. However, intrinsic delay and process variations make it difficult to manufacture an integrated circuit with inverters having various specified switching speeds. Because intrinsic delay is approximately constant, it is difficult to determine the appropriate channel dimensions for inverters of various speeds.
Even if the channel dimensions are determined, process variations make it unlikely that the inverters will have the specified speeds. Process variations are approximately constant for all inverters on an integrated circuit. Therefore, for example, if some inverters on an integrated circuit were specified to have twice the channel width of others, and if the process variation caused an increase in channel width, the wider-channeled inverters could be less than twice as fast as those with the narrower channels. Alternatively, if the process variation caused a decrease in channel width, the wider-channeled inverters could be more than twice as fast as those with the narrower channels.
Because of the difficulty in producing inverters of various specified switching speeds, the output signals of conventional buffer/inverters may not be symmetric and complementary.